PixelForge (Basys3 Retro Graphics Engine)
SystemVerilog • VGA 640×480@60Hz • BRAM • Debug w/ ILA
- Tile/sprite renderer with deterministic timing
- Built reusable video pipeline modules
- Add metrics: Fmax, LUTs/FFs, BRAM usage
RTL / FPGA / Computer Architecture
M.S. ECE @ UCLA. I build hardware systems (SystemVerilog/Vivado), optimize performance, and care about clean engineering.
SystemVerilog
Vivado
FPGA
Computer Architecture
Python
Currently
- Building PixelForge retro graphics engine on Basys3
- Studying memory systems + architecture
- Seeking RTL/FPGA/ASIC internships
Projects
Pick 2–4 strongest. Keep each one scannable: what you built, what’s impressive, and links.
10GHz+ Cascaded PLL Synthesizer Board
RF • SPI Control • Python GUI • PCB bring-up
- Designed + validated a cascaded PLL frequency synth chain
- Automation + control via Python tooling
- Add results: phase noise / spurs / comparison to eval board
About
I’m a UCLA M.S. ECE student focused on digital design, FPGA/RTL, and computer architecture (memory systems, performance). I like projects with measurable results (timing, utilization, throughput) and clean design/verification habits.